Many applications using flash memory require high read and write throughput performance. In order to achieve high read performance it is required to have an efficient implementation which minimizes the overhead associated with a read request. That is, for example, if a host needs to read in granularity of 512 B chunks and the data is encoded in larger chunks, then every read request will incur the penalty of reading more information from flash so that error correction code (ECC) decoding is possible, allowing reliable readout to the host. If the data is encoded at the granularity of the host the codeword can be too short to provide adequate reliability when the flash memory device ages.
FIG. 1 depicts a prior art system 8 that includes a flash memory controller 10 and a flash memory device 20 that includes multiple flash memory dies 20(0)-20(N). The flash memory controller 10 includes a read/write digital signal processor (DSP) 16 which usually adapts the read thresholds so as to minimize the readout errors, and a ECC module 12 which decodes the read-out data and passes it to the host through a management and host interface module 14.
On write commands, the management and host interface module 14 translates the host request to a physical block and page address of the flash memory device 20, and sends the data to the ECC module 12 for encoding; subsequently, the encoded data is written to the flash memory device 20 in the specified location. This prior art system 8 uses a single ECC configuration throughout the lifespan of the system 8.
FIG. 6 illustrates a prior art random read performance curve 60 of system 8. The performance is measured per program erase (PE) cycles.
Curve 60 starts by a horizontal portion 61 that is followed by a negative sloped portion 62. The horizontal portion 61 indicates that the read throughput is nearly constant during the start of life and until a meaningful retention occurs.
The negative sloped portion 62 represents degradation in the read throughput that increases with the number of P/E cycles, which is usually due to increased DSP operation overhead, and soft read outs from the flash device required as the error rate increases with the retention and P/E Cycles.
Accordingly, at higher wear levels the read performance is degraded since every read operation may include a DSP operation. The DSP 16 might have to search for the optimal thresholds for sampling, or might have to perform multiple reads, so as to provide the decoder a soft input to achieve full reliability.
At the end-of-life, i.e. near Cmax 66 the DSP 16 has to perform high resolution sampling to provide soft input, with high probability, since the input raw error bit rate (RBER) is usually at its maximal value on many pages.
There is a growing need to provide an optimized tradeoff between reliability and speed of flash memory programming operations.